Intel has two additions to its supercomputing lines-- Itanium 9300 successor 9500-series (aka Poulson) processor and the first Xeon Phi coprocessors.
The 9500-series processor carries Intel Itanium Architecture (IA64 ISA) and packs 3.1 billion transistor into a 32nm die. It also doubles core count (8 from 4), carries up to 54MP of on-die memory and enables up to 2TB of low-voltage DIMMs in a 4-socket configuration.
Clock speeds are up-- from 1.73GHz and 130W power level to 2.53GHz at 170W.
Reliability, Availability and Serviceability (RAS) safeguards also see improvements, with features such as such as Instruction Replay, End-to-End Error Detection and Cache Safe.
Meanwhile the Xeon Phi is a result from the "Knights Corner" part of the Intel Many Integrated Core (MIC) project. Offering over 1 teraflop of peak double-precision performance, it is ideal for high performance computing (such as financial and life sciences simulation) workloads, complementing the current Xeon E5 processors.
Intel builds the Xeon Phi chips with its 22nm process and uses the 3D Tri-Gate transistors first seen in Ivy Bridge chips.
As Intel continues it attempts to dominate in servers, one has to wonder-- what does the future hold for Itanium and Xeon? The "Solid Mission Critical Roadmap" offers a clue. Xeon and Itanium already share a chipset and a number of features, such as the previously Itanium-RAS safeguards.
Will Intel merge x86-64 and IA64 ISA architectures? According to the "Modular Development Model," yes... but partly. The future Xeon (Haswell) and Itanium (Kittson) families will share platform ingredients, including chipsets, interconnects and memory. However Intel insists it will continue supporting Itanium, seeing it has hardware support from HP, NEC, Bull, Inspur and Huawei and software compatibility from HP-UNIX, Nonstop, OpenVMS and (of course!) Oracle.
